 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
WV3HG64M64EEU-D4 Datasheet(数据表) 6 Page - White Electronic Designs Corporation |
|
||||||||||||||||||||||||||||||
WV3HG64M64EEU-D4 Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
|
|
6 page 
WV3HG64M64EEU-D4 May 2006 Rev. 2 ADVANCED 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ICC SPECIFICATION Symbol Proposed Conditions 665 534 403 Units ICC0* Operating one bank active-precharge; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 680 640 640 mA ICC1* Operating one bank active-read-precharge; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is same as ICC4W 800 760 720 mA ICC2P** Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 64 64 64 mA ICC2Q** Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputsare STABLE; Data bus inputs are FLOATING 280 240 240 mA ICC2N** Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING 320 280 280 mA ICC3P** Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 240 280 240 mA Slow PDN Exit MRS(12) = 1 96 96 96 mA ICC3N** Active standby current; All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 440 400 400 mA ICC4W* Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 1120 960 880 mA ICC4R* Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W 1160 1000 880 mA ICC5** Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 1200 1120 1120 mA ICC6** Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs vre FLOATING; Data bus inputs are FLOATING Normal 64 64 64 mA ICC7* Operating bank interleave read current; All bank interleaVINg reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING. 1760 1760 1760 mA ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Note: *: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition. |
Chinese▼
English
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
