Rev. 0.0/Feb. 2003

17

HY5DU12422A(L)T

HY5DU12822A(L)T

HY5DU121622A(L)T

POWER-UP SEQUENCE AND DEVICE INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF

(and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent dam-

age to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT.

Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect

an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to

guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal oper-

ation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR

SDRAM requires a 200us delay prior to applying an executable command.

Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be

brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED

MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE

REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating

parameters. 200 clock cycles are required between the DLL reset and any command. During the 200 cycles of CK, for

DLL locking, executable commands are disallowed (a DESELECT or NOP command must be applied). After the 200

clock cycles, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command

for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the

DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-

MOS low state. (All the other input pins may be undefined.)

• VDD and VDDQ are driven from a single power converter output.

• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.

• VREF tracks VDDQ/2.

• A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the

input current from the VTT supply into any pin.

• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-

ship must be adhered to during power up.

2. Start clock and maintain stable clock for a minimum of 200usec.

3. After stable power and clock, apply NOP condition and take CKE high.

4. Issue Extended Mode Register Set (EMRS) to enable DLL.

5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200

cycles of clock are required for locking DLL)

6. Issue Precharge commands for all banks of the device.

Voltage description

Sequencing

Voltage relationship to avoid latch-up

VDDQ

After or with VDD

< VDD + 0.3V

VTT

After or with VDDQ

< VDDQ + 0.3V

VREF

After or with VDDQ

< VDDQ + 0.3V