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CY7C1371B 数据表(PDF) 1 Page - Cypress Semiconductor

部件名 CY7C1371B
功能描述  512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1371B 数据表(HTML) 1 Page - Cypress Semiconductor

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Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05198 Rev. **
Revised February 4, 2002
512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture
CY7C1371B
CY7C1373B
73B
Features
• Pin compatible and functionally equivalent to ZBT
devices
• Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Registered inputs for flow-thru operation
• Byte Write capability
• Common I/O architecture
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 10.0ns (for 83-MHz device)
• Single 3.3V –5% and +10% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Clock enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP and 119 BGA packages
• Burst capability – linear or interleaved burst order
• JTAG boundary scan for BGA packaging version
• Automatic power down available using ZZ mode or CE
deselect
Functional Description
The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18
synchronous flow-thru burst SRAMs, respectively designed to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1371B/
CY7C1373B is equipped with the advanced No Bus Latency™
(NoBL
) logic required to enable consecutive Read/Write
operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write/Read transitions.The CY7C1371B/CY7C1373B is pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 7.5 ns (117-MHz
device).
Write operations are controlled by the byte Write Selects
(BWSa,b,c,d for CY7C1371B and BWSa,b for CY7C1373B) and
a Write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed Write circuitry. ZZ may be tied
to LOW if it is not used.
Synchronous Chip enables (CE1, CE2, CE3 on the TQFP, CE1
on the BGA) and an asynchronous Output enable (OE)
provide for easy bank selection and output three-state control.
In order to avoid bus contention, the output drivers are
synchronously three-stated during the data portion of a Write
sequence.
CLK
Ax
CEN
WE
BWSx
CE1
CE
CE2
OE
256K X 36/
Memory
Array
Logic Block Diagram
DQx
Data-In REG.
Q
D
CE
Control
and Write
Logic
3
ADV/LD
Mode
DPx
CY7C1371
CY7C1373
AX
DQX
DPX
BWSX
512K X 18
X = 18:0
X = 19:0
X= a, b, c, d X = a, b
X = a, b
X = a, b
X = a, b, c, d
X = a, b, c, d
Selection Guide
117 MHz
100 MHz
83 MHz
Unit
Maximum Access Time
7.5
8.5
10.0
ns
Maximum Operating Current
250
225
185
mA
Maximum CMOS Standby Current
20
20
20
mA


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