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CY7C1371B 数据表(PDF) 6 Page - Cypress Semiconductor

部件名 CY7C1371B
功能描述  512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture
Download  26 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1371B 数据表(HTML) 6 Page - Cypress Semiconductor

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CY7C1371B
CY7C1373B
Document #: 38-05198 Rev. **
Page 6 of 26
Functional Overview
The CY7C1371B/CY7C1373B is a synchronous flow-thru
burst NoBL SRAM specifically designed to eliminate wait
states during Write–Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the clock enable
input signal (CEN). If CEN is HIGH, the clock signal is not
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 7.5 ns (117-MHz
device).
Accesses can be initiated by asserting chip enable(s) (CE1,
CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising
edge of the clock. If the clock enable (CEN) is active LOW and
ADV/LD is asserted LOW, the address presented to the device
will be latched. The access can be either a Read or Write
operation, depending on the status of the Write enable (WE).
Byte Write Selects can be used to conduct byte Write opera-
tions.
Write operations are qualified by the WE. All Writes are
simplified with on-chip, synchronous, self-timed Write circuitry.
A synchronous chip enable (CE1, CE2, and CE3 on the TQFP,
CE1 on the BGA) and an asynchronous OE simplify depth
expansion. All operations (Reads, Writes, and Deselects) are
pipelined. ADV/LD should be driven LOW once the device has
been deselected in order to load a new address for the next
operation.
Single Read Access
A Read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) WE is deasserted HIGH,
and 4) ADV/LD is asserted LOW. The address presented to
the address inputs is latched into the Address register and
presented to the memory core and control logic. The control
logic determines that a Read access is in progress and allows
the requested data to propagate to the output buffers. The data
is available within 6.5 ns (133-MHz device) provided OE is
active LOW. After the first clock of the Read access the output
buffers are controlled by OE and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. On the subsequent clock, another operation
(Read/Write/Deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will be three-stated immediately.
Burst Read Access
The CY7C1371B/CY7C1373B has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Access
Write access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) chip
enable(s) asserted active, and (3) WE is asserted LOW. The
address presented is loaded into the Address register. The
Write signals are latched into the Control Logic block. The data
lines are automatically three-stated regardless of the state of
the OE input signal. This allows the external logic to present
the data on DQ and DP.
On the next clock rise the data presented to DQ and DP (or a
subset for byte Write operation) inputs is latched into the
device and the Write is complete (see Write Cycle Description
table for details). Additional accesses (Read/Write/Deselect)
can be initiated on this cycle.
The data written during the Write operation is controlled by
byte Write Select signals. The CY7C1371B/CY7C1373B
provides byte Write capability that is described in the Write
Cycle Description table. Asserting the WE input with the
selected byte Write Select input will selectively write to only the
desired bytes. Bytes not selected during a byte Write operation
will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the Write opera-
tions. Byte Write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple byte Write operations.
Because the CY7C1371B/CY7C1373B are common I/O
devices, data should not be driven into the device while the
outputs are active. The OE can be deasserted HIGH before
presenting data to the DQ and DP inputs. Doing so will
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port (TAP) state machine. Sampled on the rising edge
of TCK (BGA only)
TCK
JTAG serial
clock
Serial clock to the JTAG circuit (BGA only)
32M
64M
128M
No connects. Reserved for address expansion. Pins are not internally connected.
NC
No connects. Pins are not internally connected.
DNU
Do not use pins.
Pin Definitions
Name
I/O Type
Description


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