1999 Nov 23

2

Philips Semiconductors

Product specification

16-bit transceiver/register with dual enable; 3-state

74ALVCH16652

FEATURES

• In accordance with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTE™ flow-through pin-out architecture

• Low inductance, multiple supply and ground pins for

minimum noise and ground bounce

• Direct interface with TTL levels

• All data inputs have bus hold

• Output drive capability 50 Ω transmission lines at 85 °C

• Current drive ±24 mA at 3.0 V.

DESCRIPTION

The 74ALVCH16652 consists of 16 non-inverting bus

transceiver circuits with 3-state outputs, D-type flip-flops

and control circuitry arranged for multiplexed transmission

of data directly from the data bus or from the internal

storage registers.

Data on the ‘A’ or ‘B’, or both buses, will be stored in the

internal registers, at the appropriate clock inputs

inputs.

directly go from input to output (real-time mode) or data

can be controlled by the clock (storage mode), when OE

inputs permit this operating mode.

possible.

is also possible to store data without using the internal

input.

Active bus hold circuitry is provided to hold unused or

floating data inputs at a valid logic level.

QUICK REFERENCE DATA

Notes

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

2.6

ns

maximum clock frequency

350

MHz

input capacitance

4.0

pF

power dissipation capacitance per latch

notes 1 and 2

outputs enabled

22

pF

outputs disabled

4.0

pF