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CY7C1370B 数据表(PDF) 6 Page - Cypress Semiconductor

部件名 CY7C1370B
功能描述  512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture
Download  27 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1370B 数据表(HTML) 6 Page - Cypress Semiconductor

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CY7C1370B
CY7C1372B
Document #: 38-05197 Rev. **
Page 6 of 27
TDI
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.(BGA Only)
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port (TAP) state machine. Sampled on the rising edge
of TCK (BGA only).
TCK
JTAG serial
clock
Serial clock to the JTAG circuit (BGA only).
32M
64M
128M
No connects. Reserved for address expansion. Pins are not internally connected.
VSS
Ground
Ground for the device. Should be connected to ground of the system.
NC
No connects. Pins are not internally connected.
DNU
Do not use pins.
Pin Definitions
Name
I/O Type
Description


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