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CY7C1357A
CY7C1355A
Document #: 38-05265 Rev. *A
Page 21 of 28
Write Timing[40, 41, 42, 43, 44, 45]
Notes:
44. D(A1) represents the first input to the external address A1. D(A2) represents the first input to the external address A2; D(A2+1) represents the next input data
in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the
state of the MODE input.
45. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when WEN signal is sampled LOW when ADV/LD
is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
Switching Waveforms (continued)
CLK
CKE
R/W
ADDRESS
BWa, BWb
BWc, BWd
CE
ADV/LD
OE
DQ
A
1
A
2
D(A
1)
D(A
2)
D(A
2+1 )
D(A
2+2 )
D(A
2+3 )
D(A
2)
t
SD
t
HD
Write
Burst Write
(CKE# HIGH, eliminates
current L-H clock edge)
(Burst Wraps around
to initial state)
t
KL
t
KC
t
KH
t
S
t
H
BW(A
1)BW(A2)BW(A2+1 )
BW(A
2)
BW(A
2+2 )
BW(A
2+3 )
Write
Deselect
t
S
t
S
t
S
t
S
t
S
t
H
t
H
t
H
t
H
t
H
CLK
CEN
WEN
A
BWx
CE
OE
DQx
ADV/LD
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