13 / 28 page
CY7C1357A
CY7C1355A
Document #: 38-05265 Rev. *A
Page 13 of 28
ZZ
Figure 2. TAP Controller Block Diagram
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
x
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TDI
TDI
[22]
[22]
TAP Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VIH
Input High (Logic 1) Voltage[23, 24]
2.0
VCC + 0.3
V
VIl
Input Low (Logic 0) Voltage[23, 24]
–0.3
0.8
V
ILI
Input Leakage Current
0V < VIN < VCC
–5.0
5.0
µA
ILI
TMS and TDI Input Leakage Current
0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[23, 25]
IOLC = 100 µA
0.2
V
VOHC
LVCMOS Output High Voltage[23, 25]
IOHC = 100 µA
VCC – 0.2
V
VOLT
LVTTL Output Low Voltage[23]
IOLT = 8.0 mA
0.4
V
VOHT
LVTTL Output High Voltage[23]
IOHT = 8.0 mA
2.4
V
Notes:
22.X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
23. All Voltage referenced to VSS (GND).
24. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
During normal operation, VCCQ must not exceed VCC. Control input signals (such as WEN, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.).
25. This parameter is sampled.
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
