数据搜索系统,热门电子元器件搜索
  Chinese  ▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

CY7C1355A 数据表(PDF) 5 Page - Cypress Semiconductor

部件名 CY7C1355A
功能描述  256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1355A 数据表(HTML) 5 Page - Cypress Semiconductor

  CY7C1355A Datasheet HTML 1Page - Cypress Semiconductor CY7C1355A Datasheet HTML 2Page - Cypress Semiconductor CY7C1355A Datasheet HTML 3Page - Cypress Semiconductor CY7C1355A Datasheet HTML 4Page - Cypress Semiconductor CY7C1355A Datasheet HTML 5Page - Cypress Semiconductor CY7C1355A Datasheet HTML 6Page - Cypress Semiconductor CY7C1355A Datasheet HTML 7Page - Cypress Semiconductor CY7C1355A Datasheet HTML 8Page - Cypress Semiconductor CY7C1355A Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 28 page
background image
CY7C1357A
CY7C1355A
Document #: 38-05265 Rev. *A
Page 5 of 28
Pin Descriptions (CY7C1355A)
256K × 36
TQFP Pins
256K × 36
PBGA Pins
Name
Type
Description
37,
36,
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 81,
82, 83, 99, 100
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 4G, 2R,
6R, 3T, 4T, 5T
A0,
A1,
A
Input-
Synchronous
Synchronous Address Inputs: The address register is triggered by
a combination of the rising edge of CLK, ADV/LD LOW, CEN LOW
and true chip enables. A0 and A1 are the two least significant bits of
the address field and set the internal burst counter if burst cycle is
initiated.
93,
94,
95,
96
5L
5G
3G
3L
BWa,
BWb,
BWc,
BWd
Input-
Synchronous
Synchronous Byte Write Enables: Each nine-bit byte has its own
active LOW byte write enable. On load write cycles (when WEN and
ADV/LD are sampled LOW), the appropriate byte write signal (BWx)
must be valid. The byte write signal must also be valid on each cycle
of a burst write. Byte write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device one
cycle later. BWa controls DQa pins; BWb controls DQb pins; BWc
controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW
if always doing a write to the entire 36-bit word.
87
4M
CEN
Input-
Synchronous
Synchronous Clock Enable Input: When CEN is sampled HIGH, all
other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
88
4H
WEN
Input-
Synchronous
Read Write: WEN signal is a synchronous input that identifies
whether the current loaded cycle and the subsequent burst cycles
initiated by ADV/LD is a Read or Write operation. The data bus activity
for the current cycle takes place one clock cycle later.
89
4K
CLK
Input-
Clock
Clock: This is the clock input to CY7C1355A. Except for OE, ZZ, and
MODE, all timing references for the device are made with respect to
the rising edge of CLK.
98, 92
4E, 6B
CE1,
CE3
Input-
Synchronous
Synchronous Active LOW Chip Enable: CE1 and CE3 are used with
CE2 to enable the CY7C1355A. CE1 or CE3 sampled HIGH or CE2
sampled LOW, along with ADV/LD LOW at the rising edge of clock,
initiates a deselect cycle. The data bus will be High-Z one clock cycle
after chip deselect is initiated.
97
2B
CE2
Input-
Synchronous
Synchronous Active High Chip Enable: CE2 is used with CE1 and
CE3 to enable the chip. CE2 has inverted polarity but otherwise is
identical to CE1 and CE3.
86
4F
OE
Input
Asynchronous
Asynchronous Output Enable: OE must be LOW to read data.
When OE is HIGH, the I/O pins are in high-impedance state. OE does
not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied LOW.
85
4B
ADV/
LD
Input-
Synchronous
Advance/Load: ADV/LD is a synchronous input that is used to load
the internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected.
When ADV/LD is sampled HIGH, then the internal burst counter is
advanced for any burst that was in progress. The external addresses
and WEN are ignored when ADV/LD is sampled HIGH.
31
3R
MODE
Input-
Static
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst
sequence is selected. MODE is a static DC input.
64
7T
ZZ
Input-
Asynchronous
Sleep Enable: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has to
be either LOW or NC.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28 


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn