23 / 31 page
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Document #: 38-05161 Rev. *B
Page 23 of 31
Read/Write Timing[40, 43, 45, 46]
Note:
46. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2.
Switching Waveforms (continued)
CLK
CKE#
R/W#
ADDRESS
BWa#, BWb#
CE#
ADV/LD#
OE#
DATA In (D)
A
1
A
2
Write
A
3
A
4
A
5
A
6
A
7
A
8
A
9
Q(A
1)
Q(A
3)
Q(A
6)
Q(A
7)
D(A
2)
D(A
4)
D(A
5)
Write
DATA Out (Q)
Read
Read
Read
t
KQ
t
KQHZ
t
KQLZ
t
KQX
t
KL
t
KC
t
KH
BW(A
2)
t
S
t
H
BW(A
4)
BW(A
5)
t
S
t
S
t
S
t
S
t
S
t
H
t
H
t
H
t
H
t
H
CEN
WEN
BWa, BWb,
BWc, BWd
CE
OE
ADV/LD