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CY7C1354A 数据表(PDF) 2 Page - Cypress Semiconductor

部件名 CY7C1354A
功能描述  256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
Download  31 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1354A 数据表(HTML) 2 Page - Cypress Semiconductor

  CY7C1354A Datasheet HTML 1Page - Cypress Semiconductor CY7C1354A Datasheet HTML 2Page - Cypress Semiconductor CY7C1354A Datasheet HTML 3Page - Cypress Semiconductor CY7C1354A Datasheet HTML 4Page - Cypress Semiconductor CY7C1354A Datasheet HTML 5Page - Cypress Semiconductor CY7C1354A Datasheet HTML 6Page - Cypress Semiconductor CY7C1354A Datasheet HTML 7Page - Cypress Semiconductor CY7C1354A Datasheet HTML 8Page - Cypress Semiconductor CY7C1354A Datasheet HTML 9Page - Cypress Semiconductor Next Button
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CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Document #: 38-05161 Rev. *B
Page 2 of 31
.
Note:
1.
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
DQa, DQb
CLK
Input
Registers
Mux
Output Registers
Output Buffers
Address
Control
Sel
Control Logic
OE#
ZZ
MODE
CKE#
ADV/LD#
R/W#
BWa#, BWb#
CE#, CE2#, CE2
SA0, SA1, SA
OE
CEN
ADV/LD
WEN
BWa, BWb
CE, CE2, CE3
CEN
A0, A1, A
Functional Block Diagram—256K × 36[1]
DQa-DQd
CLK
Input
Registers
Mux
Output Registers
Output Buffers
Address
Control
Sel
Control Logic
OE#
ZZ
MODE
CKE#
ADV/LD#
R/W#
BWa#, BWb#
BWc#, BWd#
CE#, CE2#, CE2
SA0, SA1, SA
Functional Block Diagram—512K × 18[1]
CEN
ADV/LD
WEN
BWa, BWb,
CE, CE2, CE3
CEN
BWc, BWd
OE
A0, A1, A


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