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CY7C1354A 数据表(PDF) 5 Page - Cypress Semiconductor

部件名 CY7C1354A
功能描述  256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
Download  31 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1354A 数据表(HTML) 5 Page - Cypress Semiconductor

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CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Document #: 38-05161 Rev. *B
Page 5 of 31
Pin Descriptions—256K × 36
256K × 36
TQFP Pins
256K × 36
PBGA Pins
Pin
Name
Type
Pin Description
37,
36,
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 81,
82, 83, 99, 100
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 4G, 2R,
6R, 3T, 4T, 5T
A0,
A1,
A
Input-
Synchronous
Synchronous Address Inputs: The address register is triggered by a
combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and
true chip enables. A0 and A1 are the two least significant bits (LSBs) of
the address field and set the internal burst counter if burst cycle is
initiated.
93,
94,
95,
96
5L
5G
3G
3L
BWa,
BWb,
BWc,
BWd
Input-
Synchronous
Synchronous Byte Write Enables: Each nine-bit byte has its own
active LOW byte Write enable. On load Write cycles (when WEN and
ADV/LD are sampled LOW), the appropriate byte Write signal (BWx)
must be valid. The byte Write signal must also be valid on each cycle of
a burst Write. Byte Write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device two
cycles later. BWa controls DQa pins; BWb controls DQb pins; BWc
controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW if
always doing Writes to the entire 36-bit word.
87
4M
CEN
Input-
Synchronous
Synchronous Clock Enable Input: When CEN is sampled HIGH, all
other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
88
4H
WEN
Input-
Synchronous
Read Write: WEN signal is a synchronous input that identifies whether
the current loaded cycle and the subsequent burst cycles initiated by
ADV/LD is a Read or Write operation. The data bus activity for the
current cycle takes place two clock cycles later.
89
4K
CLK
Input-
Synchronous
Clock: This is the clock input to CY7C1354A/GVT71256ZC36. Except
for OE, ZZ and MODE, all timing references for the device are made
with respect to the rising edge of CLK.
98, 92
4E, 6B
CE,
CE3
Input-
Synchronous
Synchronous Active LOW Chip Enable: CE and CE3 are used with
CE2 to enable the CY7C1354A/GVT71256ZC36. CE or CE3 sampled
HIGH or CE2 sampled LOW, along with ADV/LD LOW at the rising edge
of clock, initiates a deselect cycle. The data bus will be High-Z two clock
cycles after chip deselect is initiated.
97
2B
CE2
Input-
Synchronous
Synchronous Active High Chip Enable: CE2 is used with CE and CE3
to enable the chip. CE2 has inverted polarity but otherwise is identical
to CE and CE3.
86
4F
OE
Input
Asynchronous Output Enable: OE must be LOW to Read data. When
OE is HIGH, the I/O pins are in high-impedance state. OE does not need
to be actively controlled for Read and Write cycles. In normal operation,
OE can be tied LOW.
85
4B
ADV/
LD
Input-
Synchronous
Advance/Load: ADV/LD is a synchronous input that is used to load the
internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected. When
ADV/LD is sampled HIGH, then the internal burst counter is advanced
for any burst that was in progress. The external addresses and WEN
are ignored when ADV/LD is sampled HIGH.
31
3R
MOD
E
Input-
Static
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst sequence
is selected. MODE is a static DC input.
64
7T
ZZ
Input-
Asynchronous
Sleep Enable: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has to be
either LOW or NC.


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