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74AHC1G125 数据表(PDF) 9 Page - NXP Semiconductors |
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74AHC1G125 数据表(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 2002 Jun 06 9 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC1G125; 74AHCT1G125 Fig.6 The 3-state enable and disable times. FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT AHC1G GND to VCC 50% VCC 50% VCC AHCT1G GND to 3.0 V 1.5 V 50% VCC handbook, full pagewidth MNA122 tPLZ tPHZ output disabled output enabled VOH −0.3 V VOL +0.3 V output enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH OE input VI VCC VM GND GND tPZL tPZH VM VM Fig.7 Load circuitry for switching times. Definitions for test circuit: CL = load capacitance including jig and probe capacitance (see Chapter “AC characteristics”). RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND handbook, full pagewidth open GND VCC VCC VI VO MNA232 D.U.T. CL RT RL = 1000 Ω PULSE GENERATOR S1 |
类似零件编号 - 74AHC1G125 |
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类似说明 - 74AHC1G125 |
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