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21285 数据表(PDF) 22 Page - Intel Corporation |
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21285 数据表(HTML) 22 Page - Intel Corporation |
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22 / 159 page  2-8 21285 Core Logic for SA-110 Datasheet Signal Description 2.7 X-Bus/Arbiter Signals The following group of pins can be configured either as a parallel port (X-Bus) or as a PCI arbiter. The configuration is determined by the value latched on ma[7] at reset. fclk_in IC Clock input for 21285. fclk_in must be connected on the circuit board to fclk (Figure 2-1). The etch length of the connection should be matched to the etch length of MCLK to the SA-110 and sdclk to the SDRAMs to minimize skew. irq_in_l[3:0] IC Interrupt inputs. These signals are general-purpose inputs that can assert nFIQ or nIRQ, can be masked, or can clock the timers. These signals are level sensitive with programmable priority and are synchronized before being used. scan_en IC Scan enable. This pin is used only in the chip manufacturing test for the internal scan chain. It must be 0 for normal operation. Figure 2-1. Clock Generation Table 2-9. Miscellaneous Signals (Sheet 2 of 2) Signal Name Type Description SA-110 MCLK osc Note: fclk to fclk_in connection on PC board. All clock etch lengths for fclk, MCLK, and sdclk should be the same. FM-05936.AI4 21285 sdclk[3:0] fclk_in fclk pci_clk 3.68 MHz Bus Frequency 4 Clocks for SDRAMs |
类似零件编号 - 21285 |
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类似说明 - 21285 |
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