Rev: 2.05 6/2000

5/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

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GS84018/32/36T/B-180/166/150/100

TQFP Pin Description

Pin Location

Symbol

Type

Description

37, 36

I

Address field LSB’s and Address Counter preset Inputs

35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,

47, 48, 49, 50

I

Address Inputs

80

I

Address Inputs (x18 versions)

52, 53, 56, 57, 58, 59, 62, 63

68, 69, 72, 73, 74, 75, 78, 79

2, 3, 6, 7, 8, 9, 12, 13

18, 19, 22, 23, 24, 25, 28, 29

I/O

Data Input and Output pins. (x32, x36 Version)

51, 80, 1, 30

I/O

Data Input and Output pins. (x36 Version)

51, 80, 1, 30

NC

No Connect (x32 Version)

58, 59, 62, 63, 68, 69, 72, 73, 74

8, 9, 12, 13, 18, 19, 22, 23, 24

I/O

Data Input and Output pins. (x18 Version)

51, 52, 53, 56, 57

75, 78, 79

1, 2, 3, 6, 7

25, 28, 29, 30

NC

-

No Connect (x18 Version)

87

BW

I

Byte Write. Writes all enabled bytes. Active Low.

93, 94

I

95, 96

I

(x32, x36 Version)

95, 96

NC

-

No Connect (x18 Version)

89

CK

I

Clock Input Signal. Active High.

88

GW

I

Global Write Enable. Writes all bytes. Active Low.

98, 92

I

Chip Enable. Active Low.

97

I

Chip Enable. Active High.

86

G

I

Output Enable. Active Low.

83

ADV

I

Burst address counter advance enable. Active Low.

84, 85

ADSP, ADSC

I

Address Strobe (Processor, Cache Controller). Active Low.

64

ZZ

I

Sleep Mode control. Active High.

14

FT

I

Flow Through or Pipeline mode. Active Low.

31

LBO

I

Linear Burst Order mode. Active Low.

15, 41, 65, 91

I

Core power supply.

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90

I

I/O and Core Ground.

4, 11, 20, 27, 54, 61, 70, 77

I

Output driver power supply.

16, 38, 39, 42, 43, 66

NC

-

No Connect.