数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

GS84036T-180 数据表(PDF) 1 Page - GSI Technology

部件名 GS84036T-180
功能描述  256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS84036T-180 数据表(HTML) 1 Page - GSI Technology

  GS84036T-180 Datasheet HTML 1Page - GSI Technology GS84036T-180 Datasheet HTML 2Page - GSI Technology GS84036T-180 Datasheet HTML 3Page - GSI Technology GS84036T-180 Datasheet HTML 4Page - GSI Technology GS84036T-180 Datasheet HTML 5Page - GSI Technology GS84036T-180 Datasheet HTML 6Page - GSI Technology GS84036T-180 Datasheet HTML 7Page - GSI Technology GS84036T-180 Datasheet HTML 8Page - GSI Technology GS84036T-180 Datasheet HTML 9Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 31 page
background image
Rev: 2.05 6/2000
1/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36T/B-180/166/150/100
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
180Mhz - 100Mhz
3.3V VDD
3.3V & 2.5V I/O
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.
Functional Description
Applications
The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version)
high performance synchronous SRAM with a 2 bit burst address
counter. Although of a type originally developed for Level 2 Cache
applications supporting high performance CPU’s, the device now
finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support. The GS84018/32/36
is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA
package.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the
BGA, ) . Holding the FT mode pin/bump low places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
SCD Pipelined Reads
The GS84018/32/36 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available.SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS84018/32/36 operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ)
pins are used to de-couple output noise from the internal circuit.
-180
-166
-150
-100
Pipeline
3-1-1-1
tCycle
tKQ
IDD
5.5ns
3.2ns
330mA
6.0ns
3.5ns
310mA
6.6ns
3.8ns
275mA
10ns
4.5ns
190mA
Flow Through
2-1-1-1
tKQ
tCycle
IDD
8ns
10ns
190mA
8.5ns
10ns
190mA
10ns
10ns
190mA
12ns
15ns
140mA


类似零件编号 - GS84036T-180

制造商部件名数据表功能描述
logo
GSI Technology
GS84036AB-100 GSI-GS84036AB-100 Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84036AB-100I GSI-GS84036AB-100I Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84036AB-150 GSI-GS84036AB-150 Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84036AB-150I GSI-GS84036AB-150I Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84036AB-166 GSI-GS84036AB-166 Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
More results

类似说明 - GS84036T-180

制造商部件名数据表功能描述
logo
GSI Technology
GS840E18T GSI-GS840E18T Datasheet
631Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840H18AT GSI-GS840H18AT Datasheet
747Kb / 30P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840FH18AT GSI-GS840FH18AT Datasheet
542Kb / 21P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840E18AT GSI-GS840E18AT Datasheet
762Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AT GSI-GS840F18AT Datasheet
554Kb / 21P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84018 GSI-GS84018 Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS880E18BT GSI-GS880E18BT Datasheet
645Kb / 28P
   512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88018T GSI-GS88018T Datasheet
1Mb / 25P
   512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
GS88018AT-250 GSI-GS88018AT-250 Datasheet
756Kb / 26P
   512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88036CGT-200 GSI-GS88036CGT-200 Datasheet
263Kb / 24P
   512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com