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GS818S18D-100 数据表(PDF) 6 Page - GSI Technology |
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GS818S18D-100 数据表(HTML) 6 Page - GSI Technology |
6 / 39 page Pin Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — NC No Connect — — R/W Read/Write Contol Pin Input Write Active Low; Read Active High NW0–NW1 Synchronous Nybble Writes Input Active Low x08 Version BW0–BW1 Synchronous Byte Writes Input Active Low x18 Version BW0–BW3 Synchronous Byte Writes Input Active Low x36 Version K Input Clock Input Active High C Output Clock Input Active High TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — K Input Clock Input Active Low C Output Clock Output Active Low DOFF DLL Disable — Active Low LD Synchronous Load Pin — Active Low CQ Output Echo Clock Output Active Low CQ Output Echo Clock Output Active High Dn Synchronous Data Inputs Input Qn Synchronous Data Outputs Output VDD Power Supply Supply 1.8 V Nominal VDDQ Isolated Output Buffer Supply Supply 1.8 or 1.5 V Nominal VSS Power Supply: Ground Supply — Notes: 1. C, C, K, or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. NC = Not Connected to die or any other pin Preliminary GS8342S08/09/18/36E-333/300/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.02 8/2005 6/39 © 2003, GSI Technology |
类似零件编号 - GS818S18D-100 |
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类似说明 - GS818S18D-100 |
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