数据搜索系统,热门电子元器件搜索 |
|
GS8170LW72AGC-333 数据表(PDF) 7 Page - GSI Technology |
|
GS8170LW72AGC-333 数据表(HTML) 7 Page - GSI Technology |
7 / 32 page GS8170LW36/72AC-350/333/300/250 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.04 4/2005 7/32 © 2003, GSI Technology Two Byte Write Control Example with Late Write SigmaRAM Special Functions Burst Cycles SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. DA DB DE DA DC F /E1 Write BC D ADV ADV Non-Write Write Write CK Address A E Write CQ /BA /BB DQA0-DQA8 DQB0-DQB8 |
类似零件编号 - GS8170LW72AGC-333 |
|
类似说明 - GS8170LW72AGC-333 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |