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GS841E18AGT-150 数据表(PDF) 5 Page - GSI Technology |
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GS841E18AGT-150 数据表(HTML) 5 Page - GSI Technology |
5 / 21 page GS841E18AT/B-180/166/150/130/100 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03 4/2005 5/21 © 2001, GSI Technology PBGA Pin Description Symbol Description An Address Input Signals—Inputs are registered and must meet setup and hold times, as specified on page 11. CLK Clock Input Signal BWE Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the four byte write signals for a write operation to occur. BW1 Byte Write signal for data outputs 1 thru 8 BW2 Byte Write signal for data outputs 9 thru 16 GW Global Write Enable CE1,CE2, CE3 Chip Enables OE Output Enable ADV Burst address advance ADSP, ADSC Address status signals DQ Data Input and Output pins DQP Parity Input and Output pins MATCH Match Output MOE Match Output Enable DE Data Enable—Data input registers are updated only when DE is active. ZZ Power down control—Application of ZZ will result in a low standby power consumption. FT Flow Through or Pipeline mode LBO Linear Order Burst mode TMS Test Mode Select TDI Test Data In TDO Test Data Out TCK Test Clock VDD 3.3 V power supply VSS Ground VDDQ 2.5 V/3.3 V output power supply NC No Connect |
类似零件编号 - GS841E18AGT-150 |
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类似说明 - GS841E18AGT-150 |
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