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MC33397R2 数据表(PDF) 7 Page - Freescale Semiconductor, Inc

部件名 MC33397R2
功能描述  Dual/Hex Low-Side Switch with Both SPI and Parallel Input Control
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MC33397R2 数据表(HTML) 7 Page - Freescale Semiconductor, Inc

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33397
7
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V
≤ VDD ≤ 5.25 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUT TIMING
Output Rise Time
VPWR=14 V, RLOAD=25 Ω, 20–80%
tR
1.0
1.2
10
µs
Output Fall Time
VPWR=14 V, RLOAD=25 Ω, 80–20%
tF
1.0
2.0
10
µs
Output Turn-On Propagation Delay
tPON
1.0
4.0
10
µs
Output Turn-Off Propagation Delay
tPOFF
1.0
4.0
10
µs
FAULT TIMING
Output Short-to-Battery Fault Filter Time
tSS
30
50
90
µs
Output Refresh Timer
tREF
3.0
4.1
6.0
ms
Output Refresh Timer Duty Cycle
D
0.2
1.56
3.0
%
Output Off-State Open Circuit Fault Filter Time
tOOF
30
50
90
µs
SPI/MISCELLANEOUS TIMING
SO Disable Time (10 K Pull-Up Resistor on SO)
CS=0.8 V to SO > 0.8*VDD
tSODIS
80
110
ns
SO Enable Time (10 K Pull-Up Resistor on SO)
CS=0.8 V to SO Low Impedance
tSOEN
80
110
ns
SO Rise Time
CL < 200 pF
tSORISE
–30
50
ns
SO Fall Time
CL < 200 pF
tSOFALL
–30
50
ns
SO Valid Time
Falling Edge of SCLK to SO Valid
tVALID
–65
80
ns
Required Time Between Falling Edge of CS to Rising Edge of
SCLK
tLEAD
100
140
ns
Required TIme Between Rising Edge of CS to Falling Edge of
SCLK
tLAG
–0
50
ns
Required Time Between SI to Rising Edge of SCLK
tSU
–25
45
ns
POR/EN Wake-Up Timer
tPOR
20
40
60
µs
Mode Change Timer (P2)
tMODE
5.0
10
25
µs
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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