NCP1308

http://onsemi.com

8

The DSS behavior actually depends on the internal IC

consumption and the MOSFET’s gate charge Qg. If we

select a MOSFET like the MTP2N60E, Qg equals 22 nC

(max). With a maximum switching frequency selected at

75 kHz, the average power necessary to drive the MOSFET

(excluding the driver efficiency and neglecting various

Qg = MOSFET’s gate charge

To obtain the output current, simply divide this result by

power consumption at no−load will therefore heavily rely

on the internal IC consumption plus the above driving

current (altered by the driver’s efficiency). Suppose that

the IC is supplied from a 350 VDC line. The current

flowing through Pin 8 is a direct image of the NCP1308

consumption (neglecting the switching losses of the HV

°C, then

the power dissipated (lost) by the IC is simply:

350 V x 2.3 mA = 805 mW. For design and reliability

reasons, it would be interesting to reduce this source of

wasted power that increases the die temperature. This can

be achieved by using different methods:

1. Use a MOSFET with lower gate charge Qg

2. Connect a diode to the half−wave portion to

directly supply the HV pin:

Figure 13. The Connection to the Half−Wave Signal

Reduces the Dissipated Power on the Controller

1

8

2

3

4

6

5

7

Cbulk

1N4007

MAINS

HV

12

5

6

with an auxiliary winding. It will automatically

disconnect the internal startup source and the IC

will be fully self−supplied from this winding.

Again, the total power drawn from the mains will

significantly decrease. Make sure the auxiliary

voltage never exceeds the 16 V limit. When the

power supply is switched off, an internal

comparator makes sure that all output pulses are

Skipping Cycle Mode

The NCP1308 automatically skips switching cycles

when the output power demand drops below a given level.

This is accomplished by monitoring the FB pin. In normal

operation, Pin 2 imposes a peak current accordingly to the

load value. If the load demand decreases, the internal loop

asks for less peak current. When this setpoint reaches a

determined level, the IC prevents the current from

decreasing further down and starts to blank the output

pulses: the IC enters the so−called skip cycle mode, also

named controlled burst operation. The power transfer now

depends upon the width of the pulse bunches (Figure 14)

and

follows

the

following

formula:

1

2 @

Lp

Lp = primary inductance

Ip = peak current at which skip cycle occurs

Figure 14. The Skip Cycle Takes Place at Low Peak

Currents which Guarantees Noise−Free Operation

0

300

200

100

MAX PEAK

CURRENT

WIDTH

RECURRENCE

SKIP CYCLE

CURRENT LIMIT

NORMAL CURRENT

MODE OPERATION

+

−

RESET

DRIVER

+

DRIVER = HIGH ? I = 0

DRIVER = LOW ? I = 200

mA

2

3

Figure 15. A Patented Method Allows for Skip

Level Selection via a Series Resistor Inserted in

Series with the Current