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QL8X12B Datasheet(数据表) 1 Page - List of Unclassifed Manufacturers

部件型号  QL8X12B
说明  Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
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制造商  ETC1 [List of Unclassifed Manufacturers]
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标志 ETC1 - List of Unclassifed Manufacturers

QL8X12B Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers

  QL8X12B 数据表 HTML 1Page - List of Unclassifed Manufacturers QL8X12B 数据表 HTML 2Page - List of Unclassifed Manufacturers QL8X12B 数据表 HTML 3Page - List of Unclassifed Manufacturers QL8X12B 数据表 HTML 4Page - List of Unclassifed Manufacturers QL8X12B 数据表 HTML 5Page - List of Unclassifed Manufacturers QL8X12B 数据表 HTML 6Page - List of Unclassifed Manufacturers QL8X12B 数据表 HTML 7Page - List of Unclassifed Manufacturers QL8X12B 数据表 HTML 8Page - List of Unclassifed Manufacturers QL8X12B 数据表 HTML 9Page - List of Unclassifed Manufacturers Next Button
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8-7
Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
Military 5.0V pASIC 1 Family
Rev B
Military 5.0V pASIC 1 Family
Device Highlights
Very High Speed
s
ViaLink“ metal-to-metal programmable technol-
ogy, allows counter speeds over 150 MHz and
logic cell delays of under 2 ns at 5V, and over 80
MHz at 3.3V operation.
High Usable Density
s
Up to a 24-by-32 array of 768 logic cells provides
22,000 usable PLD gates in 208-pin PQFP and
208-pin CQFP packages.
PCI-Output Drive
s
Fully PCI 2.1 compliant input/output capability.
(including drive current)
Features
s
Total of 180 I/O pins
s
-172 Bidirectional Input/Output pins
s
-6 Dedicated Input/High-Drive pins
s
-2 Clock/Dedicated input pins with fanout-
independent, low-skew clock networks
s
-PCI 2.1 Compliant I/Os
s
Input + logic cell + output delays under 6 ns
s
Chip-to-chip operating frequencies up to 110 MHz
s
Internal state machine frequencies up to 150 MHz
s
Clock skew < 0.5 ns
s
Input hysteresis provides high noise immunity
s
Built-in scan path permits 100% factory testing of
logic and I/O cells and functional testing with Auto-
matic Test Vector Generation (ATVG) software
after programming
s
208 pin PQFP pin for pin compatible with the
208 CQFP
s
0.65µ CMOS process with ViaLink programming
technology
TABLE 1: Selector Table
DEVICE HIGHLIGHTS
FEATURES
Device
ASIC
Gates
PLD
Gates
Package
Max
I/O
Qualification
Level
SMD
5962-
QL8x12B
1,000
2,000
68CPGA
64
M
QL12x16B
2,000
4,000
84CPGA
76
M, /883
96836
144CPGA
122
M, /883
95599
QL16x24B
4,000
7,000
160 CQFP
122
M, /883
95599
208CQFP
180
M, /883
96837
QL24x32B
8,000
14,000
208PQFP
180
M
M = Military Temperature (-55 to +125 degrees C)
/883 = MIL-STD-883 qualified




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