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QL8X12B Datasheet(数据表) 2 Page - List of Unclassifed Manufacturers

部件型号  QL8X12B
说明  Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
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制造商  ETC1 [List of Unclassifed Manufacturers]
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QL8X12B Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

 
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8
Preliminary
8-8
Military 5.0V pASIC 1 Family
Product Summary
The pASIC 1 Family is a very-high-speed CMOS
user-programmable ASIC devices. The 768 logic cell
field-programmable gate array (FPGA) features
22,000 usable PLD gates of high-performance gen-
eral-purpose logic in a 208-pin PQFP and CQFP
package.
Low-impedance, metal-to-metal, ViaLink intercon-
nect technology provides nonvolatile custom logic
capable of operating above 150 MHz. Logic cell
delays under 2 ns, combined with input delays of
under 1.5 ns and output delays under 3 ns, permit
high-density programmable devices to be used with
today’s fastest microprocessors and DSPs.
Designs can be entered using QuickLogic’s Quick-
Works Toolkit or most popular third-party CAE tools.
QuickWorks combines Verilog/VHDL design entry
and simulation tools with device-specific place &
route and programming software. Ample on-chip
routing channels allow fast, fully automatic place and
route of designs using up to 100% of the logic and I/
O cells, while maintaining fixed pin-outs.
Pinout Diagram 68-Pin CPGA
TABLE 2: CPGA 68 Function/Connector Pin Table
PRODUCT SUMMARY
PINOUT DIAGRAM 68-PIN CPGA
PIN
FUNC
PIN
FUNC
PIN
FUNC
PIN
FUNC
B10
IO
B2
IOK2
IOK10
IO
A10
IO
B1
IO
L2
IO
K11
IO
B9
IO
C2
IO
K3
IO
J10
IO
A9
IO
C1
IO
L3
IO
J11
IO
B8
IO
D2
IO
K4
IO
H10
IO
A8
IO
D1
IO
L4
IO
H11
IO
B7
I/(SCLK)
E2
IO
K5
I/(SI)
G10
IO
A7
I/CLK/(SM)
E1
IO
L5
I/CLK
G11
IO
B6
VCC
F2
GND
K6
VCC
F10
GND
A6
I
F1
IO
L6
I
F11
IO
B5
I
G2
IO
K7
I/(SO)
E10
IO
A5
IO
G1
IO
L7
IO
E11
IO
B4
IO
H2
IO
K8
IO
D10
IO
A4
IO
H1
IO
L8
IO
D11
IO
B3
IO
J2
IO
K9
IO
C10
IO
A3
IO
J1
IO
L9
IO
C11
IO
A2
IO
K1
IO
L10
IO
B11
IO




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