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SN74AUCH16374DGGR 数据表(PDF) 5 Page - Texas Instruments |
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SN74AUCH16374DGGR 数据表(HTML) 5 Page - Texas Instruments |
5 / 12 page SN74AUCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES404D – JULY 2002 – REVISED MAY 2003 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V UNIT TYP MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency 85 250 250 250 250 MHz tw Pulse duration, CLK high or low 5.9 1.9 1.9 1.9 1.9 ns tsu Setup time, data before CLK ↑ 1.4 1.2 0.7 0.6 0.6 ns th Hold time, data after CLK ↑ 0.1 0.4 0.4 0.4 0.4 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX fmax 85 250 250 250 250 MHz tpd CLK Q 7.3 1 4.5 0.8 2.9 0.7 1.5 2.8 0.7 2.2 ns ten OE Q 7 1.2 5.3 0.8 3.6 0.8 1.5 2.9 0.7 2.2 ns tdis OE Q 8.2 2 7.1 1 4.8 1.4 2.7 4.5 0.5 2.2 ns operating characteristics, TA = 25°C† PARAMETER TEST VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V UNIT PARAMETER CONDITIONS TYP TYP TYP TYP TYP UNIT Cpd‡ (each output) Power dissipation capacitance Outputs enabled, 1 output switching 1 fdata = 5 MHz 1 fclk = 10 MHz 1 fout = 5 MHz OE = GND CL = 0 pF 24 24 24.1 26.2 31.2 pF Cpd (Z) Power dissipation capacitance Outputs disabled, 1 clock and 1 data switching 1 fdata = 5 MHz 1 fclk = 10 MHz fout = not switching OE = VCC CL = 0 pF 7.5 7.5 8 9.4 13.2 pF Cpd§ (each clock) Power dissipation capacitance Outputs disabled, clock only switching 1 fdata = 0 MHz 1 fclk = 10 MHz fout = not switching OE = VCC CL = 0 pF 13.8 13.8 14 14.7 17.5 pF † Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}. ‡ Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz in this test, but its ICC component has been subtracted out). § Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz. |
类似零件编号 - SN74AUCH16374DGGR |
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类似说明 - SN74AUCH16374DGGR |
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