SMS46GR07 datasheet(11/17 Pages) SUMMIT

部件名	SMS46GR07

功能描述	Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory

Download	17 Pages

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制造商	SUMMIT [Summit Microelectronics, Inc.]

网页	http://www.summitmicro.com

标志

11 / 17 page

11

2083 1.1 06/04/04

SMS46

SUMMIT MICROELECTRONICS, Inc.

Preliminary Information

Table 8. Memory Operating Characteristics

2047 Table10 4.0

Figure 7 - Memory Operating Characteristics

I2C INTERFACE

Note (1): These values are guaranteed by design.

MEMORY OPERATION

Data for the configuration registers and the memory array

are read and written via an industry standard two-wire

interface. The bus was designed for two-way, two-line

serial communication between different integrated cir-

cuits. The two lines are a serial data line (SDA) and a

serial clock line (SCL). The SDA line must be connected

to a positive supply by a pull-up resistor, located some-

where on the bus. See Memory Operating Characteris-

tics: Table 8 and Figure 7.

Input Data Protocol

The protocol defines any device that sends data onto the

bus as a transmitter and any device that receives data as

a receiver. The device controlling data transmission is

called the Master and the controlled device is called the

Slave. In all cases the SMS46 will be a Slave device, since

it never initiates any data transfers.

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during clock high

time because changes on the data line while SCL is high

will be interpreted as start or stop condition.

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类似零件编号 - SMS46GR07

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