数据搜索系统,热门电子元器件搜索 |
|
SMS45GCR05 数据表(PDF) 11 Page - Summit Microelectronics, Inc. |
|
SMS45GCR05 数据表(HTML) 11 Page - Summit Microelectronics, Inc. |
11 / 20 page 11 2079 1.2 05/24/04 SMS45 SUMMIT MICROELECTRONICS, Inc. Preliminary Information Table 5. Configuration Register 6 (D3 through D7) Note 1 - Read Only bit D7 is set to a 0. Read only bits D4 and D3 are revision control and the value indi- cates the status code of the device (ie. 01 is status code 1). Table 4. Configuration Register 5 (D4 through D7) Table 3. Configuration Register 5 (D0 through D3) The delay from VPTH0 until PUP#1 low is tPDLY1. There is a similar tPDLYX delay for V1 to PUP#2 and for V2 to PUP#3. They are programmed in register 7. Cascading will always occur as indicated in the flow chart (Figure 7). WATCHDOG TIMER The Watchdog Timer will generate a reset if it times out. It can be cleared by a high-to-low transition on WLDI and restarted. If the Watchdog times out RESET# will be driven low until tPRTO at which time it will return high. Refer to Figure 4 which illustrates the action of RESET# with respect to the Watchdog timer and the WLDI input. If WLDI is held low the timer will free-run generating a series of resets. When the Watchdog times out RESET# will be generated. When RESET# returns high (after tPRTO) the timer is reset to time zero. Register 6 is also used to set the programmable reset time- out period (tPRTO) and to select the cascade option. Cascade Delay Programming The cascade delays are programmed in register 7. Bit 7 of register 6 must be set to a 0 in order to enable the cascading of the PUP# outputs. Cascading will not commence until V0 is above its programmed threshold. Each PUP# (-3, -2 and -1) is delayed according to the states of its Bit 1 and Bit 0 as indicated in Table 9. Refer to Figures 1 and 5 for the detailed timing relationship of the program- mable power-on cascading. Table 6. Configuration Register 6 (D0, D1, D2) n o i t c A 3 D B S M 2 D1 D 0 D B S L V 3 V 2 V 1 V 0 s e l b a n e 0 a g n i t i r W r o f n o i t c e t e d e g a t l o v r e d n u t u p n i V d e t c e l e s e h t 0000 s e l b a n e 1 a g n i t i r W r o f n o i t c e t e d e g a t l o v r e v o t u p n i V d e t c e l e s e h t 1111 7 D B S M 6 D5 D4 D3 D d a e R 1 y l n O 1 O T R0 O T R d a e R y l n O d a e R y l n O n o i t c A 00 0 xx t O T R P s m 5 2 = 00 1 xx t O T R P s m 0 5 = 01 0 xx t O T R P s m 0 0 1 = 01 1 xx t O T R P s m 0 0 2 = 7 D B S M 6 D5 D 4 D B S L n o i t c A V 3 V 2 V 1 V 0 0000 a s e t a c i d n i 1 a g n i d a e R t l u a f y l p p u s 1111 CONFIGURATION REGISTERS (CONTINUED) 2 D1 D 0 D B S L n o i t c A2 D W1 D W0 D W F F O 000 s m 0 0 40 1 1 s m 0 0 81 0 0 s m 0 0 6 11 0 1 s m 0 0 2 31 1 0 s m 0 0 4 6 111 |
类似零件编号 - SMS45GCR05 |
|
类似说明 - SMS45GCR05 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |