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SMM105 数据表(PDF) 4 Page - Summit Microelectronics, Inc. |
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SMM105 数据表(HTML) 4 Page - Summit Microelectronics, Inc. |
4 / 21 page SMM105 Preliminary Information Summit Microelectronics, Inc 2068 1.8 09/20/05 4 PIN DESCRIPTIONS QFN Pad Number Ultra CSP TM Ball Number Pin Type Pin Name Pin Description 28 A3 DATA SDA I 2C Bi-directional data line 1 A1 CLK SCL I 2C clock input. 2 A2 I A2 4 B2 I A1 6 C2 I A0 The address pins are biased either to VDD_CAP or GND. When communicating with the SMM105 over the 2-wire bus these pins provide a mechanism for assigning a unique bus address. 8 E1 I WP# Write Protect active low input. When asserted, writes to the configuration registers and general purpose EE are not allowed. 10 E2 CAP FILT_CAP External capacitor input used to filter the VM input. 18 C5 CAP TRIM_CAP External capacitor input used for Active Control and margining. 20 B5 O TRIM Output voltage used to control and/or margin converter voltages. Connect to the converter trim input. 14 E4 I VM Voltage monitor input. Connect to the DC-DC converter positive sense line or its’ +Vout pin. 9 D2 I VREF_CNTL Voltage reference input used for DC output control and margining. VREF_CNTL can be programmed to output the internal 1.25V reference. Pin should be left open if using VREF internal 21 B4 PWR VDD Power supply of the part. 7 D1 GND GND Ground of the part. The SMM105 ground pin should be connected to the ground of the device under control or to a star point ground. PCB layout should take into consideration ground drops. 22 A5 PWR 12VIN 12V power supply input internally regulated to either 3.6V or 5.5V. When using the 3.6V internal regulator option, the 12VIN input can be as low as 8V. It can be as high as 15V using the 5.5V internal regulator. 3 B1 I START Programmable active high/low input. The START input is used solely for enabling Active Control and/or margining. There is also a programmable start delay time, TSTART to delay ADOC/Margin control. 5 C1 I/O READY Programmable active high/low open drain output indicates that VM is at its set point. When programmed as an active high output, READY can also be used as an input. When pulled low, it will latch the state of the comparator inputs. 23 A4 CAP VDD_CAP External capacitor input used to filter the internal supply rail. 19 C4 I COMP1 12 E3 I COMP2 COMP1 and COMP2 are high impedance inputs, each connected internally to a comparator and compared against the VREF_CNTL input. Each comparator can be independently programmed to monitor for UV or OV. The monitor level is set externally with a resistive voltage divider. 11 D3 O FAULT# When either of the COMP1 or COMP2 inputs are in fault the open- drain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output while the device is margining. 13,15,16 17,24-27 B3,C3, D4,D5, E5 NC NC No Connect. Leave floating; do not connect anything to the NC pins. |
类似零件编号 - SMM105 |
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类似说明 - SMM105 |
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