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DSPIC30F0013AT-30IPT-ES 数据表(PDF) 60 Page - Microchip Technology |
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DSPIC30F0013AT-30IPT-ES 数据表(HTML) 60 Page - Microchip Technology |
60 / 220 page dsPIC30F3014/4013 DS70138C-page 58 Advance Information 2004 Microchip Technology Inc. 8.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 8-1. They are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. Note that many of these trap conditions can only be detected when they occur. Consequently, the question- able instruction is allowed to complete prior to trap exception processing. If the user chooses to recover from the error, the result of the erroneous action that caused the trap may have to be corrected. There are 8 fixed priority levels for traps: Level 8 through Level 15, which implies that the IPL3 is always set during processing of a trap. If the user is not currently executing a trap, and he sets the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all interrupts are disabled, but traps can still be processed. 8.3.1 TRAP SOURCES The following traps are provided with increasing prior- ity. However, since all traps can be nested, priority has little effect. Math Error Trap: The Math Error trap executes under the following three circumstances: 1. Should an attempt be made to divide by zero, the divide operation will be aborted on a cycle boundary and the trap taken. 2. If enabled, a Math Error trap will be taken when an arithmetic operation on either accumulator A or B causes an overflow from bit 31 and the accumulator guard bits are not utilized. 3. If enabled, a Math Error trap will be taken when an arithmetic operation on either accumulator A or B causes a catastrophic overflow from bit 39 and all saturation is disabled. 4. If the shift amount specified in a shift instruction is greater than the maximum allowed shift amount, a trap will occur. Address Error Trap: This trap is initiated when any of the following circumstances occurs: 1. A misaligned data word access is attempted. 2. A data fetch from our unimplemented data memory location is attempted. 3. A data access of an unimplemented program memory location is attempted. 4. An instruction fetch from vector space is attempted. 5. Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where literal is an unimplemented program memory address. 6. Executing instructions after modifying the PC to point to unimplemented program memory addresses. The PC may be modified by loading a value into the stack and executing a RETURN instruction. Stack Error Trap: This trap is initiated under the following conditions: 1. The stack pointer is loaded with a value which is greater than the (user programmable) limit value written into the SPLIM register (stack overflow). 2. The stack pointer is loaded with a value which is less than 0x0800 (simple stack underflow). Oscillator Fail Trap: This trap is initiated if the external oscillator fails and operation becomes reliant on an internal RC backup. 8.3.2 HARD AND SOFT TRAPS It is possible that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the fixed priority shown in Figure 8-2 is implemented, which may require the user to check if other traps are pending, in order to completely correct the fault. ‘Soft’ traps include exceptions of priority level 8 through level 11, inclusive. The arithmetic error trap (level 11) falls into this category of traps. ‘Hard’ traps include exceptions of priority level 12 through level 15, inclusive. The address error (level 12), stack error (level 13) and oscillator error (level 14) traps fall into this category. Note: If the user does not intend to take correc- tive action in the event of a trap error condition, these vectors must be loaded with the address of a default handler that simply contains the RESET instruction. If, on the other hand, one of the vectors containing an invalid address is called, an address error trap is generated. Note: In the MAC class of instructions, wherein the data space is split into X and Y data space, unimplemented X space includes all of Y space, and unimplemented Y space includes all of X space. |
类似零件编号 - DSPIC30F0013AT-30IPT-ES |
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类似说明 - DSPIC30F0013AT-30IPT-ES |
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