6
SMS2916
2028-02 4/24/98
Preliminary
The RESET pins are I/Os; therefore, the SMS2916 can
act as a signal conditioning circuit for an externally
applied reset. The inputs are edge triggered; that is, the
RESET input will initiate a reset timeout after detecting a
low to high transition and the
RESET input will initiate a
reset timeout after detecting a high to low transition. Refer
to the applications Information section for more details on
device operation as a reset conditioning circuit.
WATCHDOG TIMER OPERATION
The SMS2916 has a watchdog timer with a nominal
timeout period of 1.6 seconds. Whenever the watchdog
times out it will generate a reset output on both
RESET
and RESET. There are two methods of clearing the
watchdog timer; the first is through the use of software,
and the second is by strobing the WDI input pin.
Software Method
The watchdog timer will clear to t0 whenever the
SMS2916 issues an ACKnowledge. Therefore, the host
system will need to issue a start condition, followed by a
valid address and command. It can be a normal com-
mand as in the sequence of reading or writing to the
memory, or it can be a dummy command issued solely for
the purpose of resetting the watchdog timer. Refer to
Figure 12 for detailed sequence of operations.
The watchdog timer will be held in the cleared state during
power-on while VCC is less than VTRIP. Once VCC ex-
ceeds VTRIP the watchdog will continue to be held in a
cleared state for the duration of tPURST. After tPURST, the
timer will be released and begin counting.
If either reset input is asserted the watchdog timer will be
cleared and remain in the reset condition until either
tPURST has expired or the reset input is released, which-
ever is longer.
If the watchdog times out and no action is taken by the
host the SMS2916 will drive the reset outputs active for
the duration of tPURST at which point it will release the
outputs and clear the watchdog timer again and release
it to begin a new count. Refer to Figure 13 for detailed
sequence of operations.
Hardware Method
A high to low transition on
WDI will clear the watchdog
timer. If a transition is not detected within 1.6 seconds the
watchdog will time out and force the reset outputs active.
PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
RESET
RESET
RESET
RESET
RESET - RESET is an active low output. Whenever VCC
is below VTRIP the SMS2916 will drive the RESET pin to
ground. The
RESET pin is an I/O and can be used as a
reset input. Refer to Figure 1 as an example use of this pin
as a push button switch debounce circuit. It should be
noted this is an open drain output and an external pull-up
resistor tied to VCC is needed for proper operation.
RESET — RESET is an active high output. Whenever
VCC is below VTRIP the SMS2916 will drive the RESET pin
to the VCC rail. The RESET pin is an I/O and can be used
as a reset input. It should be noted this is an open drain
output and an external pull-down resistor tied to ground is
needed for proper operation.
WDI
WDI
WDI
WDI
WDI - The WDI input is used as a hardware method of
clearing the watchdog timer. A high to low transition on
this pin will clear the watchdog timer. If a transition is not
detected within 1.6 seconds the watchdog will time out
and force the reset outputs active.
ENDURANCE AND DATA RETENTION
The SMS2916 is designed for applications requiring
1,000,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 1,000,000
erase/write cycles.
Reset Controller Description
The SMS2916 provides a precision RESET controller that
ensures correct system operation during brown-out and
power-up/-down conditions. It is configured with two open
drain RESET outputs; pin 7 is an active high output and
pin 2 is an active low output.
During power-up, the RESET outputs remain active until
VCC reaches the VTRIP threshold and will continue driving
the outputs for approximately 200ms after reaching VTRIP.
The RESET outputs will be valid so long as VCC is > 1.0V.
During power-down, the RESET outputs will begin driving
active when VCC falls below VTRIP.