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FIN3384 数据表(PDF) 8 Page - Fairchild Semiconductor |
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FIN3384 数据表(HTML) 8 Page - Fairchild Semiconductor |
8 / 18 page www.fairchildsemi.com 8 Receiver DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16) Note 16: All Typical values are at TA 25 qC and with VCC 3.3V. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except 'VOD and VOD). Note 17: The power supply current for the receiver can be different with the number of active I/O channels. Note 18: Total channel latency from Sewrializer to deserializer is (T tTCCD). There is the clock period. Note 19: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. Symbol Parameter Test Conditions Min Typ Max Units LVTTL/CMOS DC Characteristics VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage GND 0.8 V VOH Output High Voltage IOH 0.4 mA 2.7 3.3 V VOL Output Low Voltage IOL 2mA 0.06 0.3 V VIK Input Clamp Voltage IIK 18 mA 0.79 1.5 V IIN Input Current VIN 0V to 4.6V 10.0 10.0 PA IOFF Input/Output Power Off Leakage Current VCC 0V, r10.0 PA All LVTTL Inputs/Outputs 0V to 4.6V IOS Output Short Circuit Current VOUT 0V 60.0 120 mA Receiver LVDS Input Characteristics VTH Differential Input Threshold HIGH Figure 2, Table 2 100 mV VTL Differential Input Threshold LOW Figure 2, Table 2 100 mV VICM Input Common Mode Range Figure 2, Table 2 0.05 2.35 V IIN Input Current VIN 2.4V, VCC 3.6V or 0V r10.0 PA VIN 0V, VCC 3.6V or 0V r10.0 PA Receiver Supply Current ICCWR 4:28 Receiver Power Supply Current 32.5 MHz 70.0 mA for Worst Case Pattern (With Load) CL 8 pF, 40.0 MHz 75.0 (Note 17) See Figure 3 66.0 MHz 114 85.0 MHz 135 ICCWR 3:21 Receiver Power Supply Current 32.5 MHz 49.0 60.0 mA for Worst Case Pattern (With Load) CL 8 pF, 40.0 MHz 53.0 65.0 (Note 17) See Figure 3 66.0 MHz 78.0 100 85.0 MHz 90.0 115 ICCPDT Powered Down Supply Current PwrDn 0.8V (RxOut stays LOW) NA 55.0 PA tRCOP Receiver Clock Output (RxCLKOut) Period 11.76 T 50.0 tRCOL RxCLKOut LOW Time See Figure 8 4.0 5.0 6.0 ns tRCOH RxCLKOut HIGH Time (f 85MHz) 4.5 5.0 6.5 ns tRSRC RxOut Valid Prior to RxCLKOut (Rising Edge Strobe) 3.5 ns tRHRC RxOut Valid After RxCLKOut 3.5 ns tROLH Output Rise Time (20% to 80%) CL 8 pF, 2.0 3.5 ns tROHL Output Fall Time (80% to 20%) See Figure 4 1.8 3.5 ns tRCCD Receiver Clock Input to Clock Output Delay See Figure 20, (Note 18) 3.5 5.0 7.5 ns TA 25qC and VCC 3.3V tRPDD Receiver Power-Down Delay See Figure 13 1.0 Ps tRSPB0 Receiver Input Strobe Position of Bit 0 0.49 0.84 1.19 ns tRSPB1 Receiver Input Strobe Position of Bit 1 2.17 2.52 2.87 ns tRSPB2 Receiver Input Strobe Position of Bit 2 3.85 4.20 4.55 ns tRSPB3 Receiver Input Strobe Position of Bit 3 See Figure 17 (f 85MHz) 5.53 5.88 6.23 ns tRSPB4 Receiver Input Strobe Position of Bit 4 7.21 7.56 7.91 ns tRSPB5 Receiver Input Strobe Position of Bit 5 8.89 9.24 9.59 ns tRSPB6 Receiver Input Strobe Position of Bit 6 10.57 10.92 11.27 ns tRSKM RxIN Skew Margin See Figure 17, (Note 19) 290 ps tRPLLS Receiver Phase Lock Loop Set Time See Figure 11 10.0 ms |
类似零件编号 - FIN3384 |
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类似说明 - FIN3384 |
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