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EZ80L92AZ050EG 数据表(PDF) 26 Page - Zilog, Inc. |
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EZ80L92AZ050EG 数据表(HTML) 26 Page - Zilog, Inc. |
26 / 241 page PS013012-1004 PRELIMINARY Architectural Overview eZ80L92 MCU Product Specification 11 47 RD Read Output, Active Low RD Low indicates that the eZ80L92 MCU is reading from the current address location. This pin is tristated during bus acknowledge cycles. 48 WR Write Output, Active Low WR indicates that the CPU is writing to the current address location. This pin is tristated during bus acknowledge cycles. 49 INSTRD Instruction Read Indicator Output, Active Low INSTRD (with MREQ and RD) indicates the eZ80L92 MCU is fetching an instruction from memory. This pin is tristated during bus acknowledge cycles. 50 WAIT WAIT Request Input, Active Low Driving the WAIT pin Low forces the CPU to wait additional clock cycles for an external peripheral or external memory to complete its Read or Write operation. 51 RESET Reset Schmitt Trigger Input, Active Low This signal is used to initialize the eZ80L92 MCU. This input must be Low for a minimum of 3 system clock cycles, and must be held Low until the clock is stable. This input includes a Schmitt trigger to allow RC rise times. 52 NMI Nonmaskable Interrupt Schmitt Trigger Input, Active Low The NMI input is a higher priority input than the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. 53 BUSREQ Bus Request Input, Active Low External devices can request the eZ80L92 MCU to release the memory interface bus for their use, by driving this pin Low. 54 BUSACK Bus Acknowledge Output, Active Low The eZ80L92 MCU responds to a Low on BUSREQ, by tristating the address, data, and control signals, and by driving the BUSACK line Low. During bus acknowledge cycles ADDR[23:0], IORQ, and MREQ are inputs. 55 HALT_SLP HALT and SLEEP Indicator Output, Active Low A Low on this pin indicates that the CPU has entered either HALT or SLEEP mode because of execution of either a HALT or SLP instruction. Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # Symbol Function Signal Direction Description |
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