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EZ80L92AZ020EG 数据表(PDF) 34 Page - Zilog, Inc. |
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EZ80L92AZ020EG 数据表(HTML) 34 Page - Zilog, Inc. |
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34 / 241 page  PS013012-1004 PRELIMINARY Architectural Overview eZ80L92 MCU Product Specification 19 92 PB4 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or open- source output. T4_OUT Timer 4 Out Output Programmable Reload Timer 4 timer-out signal. This signal is multiplexed with PB4. 93 PB5 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or open- source output. T5_OUT Timer 5 Out Output Programmable Reload Timer 5 timer-out signal. This signal is multiplexed with PB5. 94 PB6 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or open- source output. MISO Master In Slave Out Bidirectional The MISO line is configured as an input when the eZ80L92 MCU is an SPI master device and as an output when eZ80L92 MCU is an SPI slave device. This signal is multiplexed with PB6. Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # Symbol Function Signal Direction Description |
类似零件编号 - EZ80L92AZ020EG |
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类似说明 - EZ80L92AZ020EG |
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