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MC100ES6221TB 数据表(PDF) 2 Page - Freescale Semiconductor, Inc |
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MC100ES6221TB 数据表(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 12 page Advanced Clock Drivers Devices 2 Freescale Semiconductor MC100ES6221 Figure 1. MC100ES6221 Logic Diagram Figure 2. 52-Lead Package Pinout (Top View) 0 1 CLK0 CLK0 CLK1 CLK1 CLK_SEL VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q16 Q16 Q17 Q17 Q18 Q18 Q19 Q19 VBB VEE VEE • • • VEE VCC • • • VCC Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 Q12 Q12 Q13 Q13 Q14 Q14 Q15 Q15 Q16 Q16 Q17 Q17 VCC 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 1 234 567 89 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MC100ES6221 Table 1. Pin Configuration Pin I/O Type Function CLK0, CLK0 Input ECL/PECL Differential reference clock signal input CLK1, CLK1 Input HSTL Alternative differential reference clock signal input CLK_SEL Input ECL/PECL Reference clock input select QA[0–19], QA[0–19] Output ECL/PECL Differential clock outputs VEE(1) 1. In ECL mode (negative power supply mode), VEE is either –3.3 V or –2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Supply Negative power supply VCC Supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. VBB Output DC Reference voltage output for single ended ECL and PECL operation Table 2. Function Table Pin 0 1 CLK_SEL CLK0, CLK0 input pair is the reference clock. CLK0 can be driven by ECL or PECL compatible signals. CLK1, CLK1 input pair is the reference clock. CLK1 can be driven by HSTL compatible signals. |
类似零件编号 - MC100ES6221TB |
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类似说明 - MC100ES6221TB |
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