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MC100ES6221 数据表(PDF) 9 Page - Freescale Semiconductor, Inc |
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MC100ES6221 数据表(HTML) 9 Page - Freescale Semiconductor, Inc |
9 / 12 page Advanced Clock Drivers Devices Freescale Semiconductor 9 MC100ES6221 APPLICATIONS INFORMATION Using the Thermally Enhanced Package of the MC100ES6221 The MC100ES6221 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the lead frame is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES6221 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6221. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6221 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as shown in Figure 6, providing an efficient heat removal path. Figure 6. Recommended Thermal Land Pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 7 shows a recommend solder mask opening with respect to the recommended 3 x 3 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 7. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. Figure 7. Recommended Solder Mask Openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6221 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern all units mm Table 9. Thermal Resistance(1) 1. Applicable for a 3 x 3 thermal via array. ConvectionL FPM RTHJA (2) °C/W 2. Junction to ambient, four conductor layer test board (2S2P), per JES51–7 and JESD 51–5. RTHJA (3) °C/W 3. Junction to ambient, single layer test board, per JESD51–3. RTHJC °C/W RTHJB (4) °C/W 4. Junction to board, four conductor layer test board (2S2P) per JESD 51–8. Natural 20 48 4(5) 29(6) 5. Junction to exposed pad. 6. Junction to top of package. 16 100 18 47 200 17 46 400 16 43 800 15 41 Exposed pad land pattern 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter 1.0 0.2 all units mm |
类似零件编号 - MC100ES6221 |
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类似说明 - MC100ES6221 |
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