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EP1C20F400I8 数据表(PDF) 77 Page - Altera Corporation |
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EP1C20F400I8 数据表(HTML) 77 Page - Altera Corporation |
77 / 94 page Altera Corporation 77 Preliminary Information Cyclone FPGA Family Data Sheet Internal timing parameters are specified on a speed grade basis independent of device density. Tables 44 through 47 show the internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 44. LE Internal Timing Microparameters Symbol -6 -7 -8 Unit MinMax MinMax MinMax tSU 29 33 37 ps tH 12 13 15 ps tCO 173 198 224 ps tLUT 454 522 590 ps tCLR 129 148 167 ps tPRE 129 148 167 ps tCLKHL 107 123 139 ps Table 45. IOE Internal Timing Microparameters Symbol -6 -7 -8 Unit MinMax MinMax MinMax tSU 98 107 117 ps tH 65 71 78 ps tCO 161 177 193 ps tPIN2COMBOUT_R 1,107 1,217 1,328 ps tPIN2COMBOUT_C 1,112 1,223 1,334 ps tCOMBIN2PIN_R 2,776 3,053 3,331 ps tCOMBIN2PIN_C 2,764 3,040 3,316 ps tCLR 280 308 336 ps tPRE 280 308 336 ps tCLKHL 95 104 114 ps |
类似零件编号 - EP1C20F400I8 |
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类似说明 - EP1C20F400I8 |
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