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EP1C12F324I8 数据表(PDF) 12 Page - Altera Corporation

部件名 EP1C12F324I8
功能描述  Cyclone FPGA Family
Download  94 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1C12F324I8 数据表(HTML) 12 Page - Altera Corporation

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Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see Figure 6). The
Quartus II Compiler automatically selects the carry-in or the data3 signal
as one of the inputs to the LUT. Each LE can use LUT chain connections to
drive its combinatorial output directly to the next LE in the LAB.
Asynchronous load data for the register comes from the data3 input of
the LE. LEs in normal mode support packed registers.
Figure 6. LE in Normal Mode
Note to Figure 6:
(1)
This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
data1
4-Input
LUT
data2
data3
cin (from cout
of previous LE)
data4
addnsub (LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
aload
(LAB Wide)
ALD/PRE
CLRN
D
Q
ENA
ADATA
sclear
(LAB Wide)
sload
(LAB Wide)
Register chain
connection
LUT chain
connection
Register
chain output
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
Register Feedback
(1)


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