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EP1C6F256I8 数据表(PDF) 24 Page - Altera Corporation |
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EP1C6F256I8 数据表(HTML) 24 Page - Altera Corporation |
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24 / 94 page  24 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Figure 13. Simple Dual-Port & Single-Port Memory Configurations Note to Figure 13: (1) Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in ×1 mode at port A and read out in ×16 mode from port B. The Cyclone memory architecture can implement fully synchronous RAM by registering both the input and output signals to the M4K RAM block. All M4K memory block inputs are registered, providing synchronous write cycles. In synchronous operation, the memory block generates its own self-timed strobe write enable (wren) signal derived from a global clock. In contrast, a circuit using asynchronous RAM must generate the RAM wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. The output registers can be bypassed. Pseudo-asynchronous reading is possible in the simple dual-port mode of M4K blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. data[] wraddress[] wren inclock inclocken inaclr rdaddress[] rden q[] outclock outclocken outaclr data[] address[] wren inclock inclocken inaclr q[] outclock outclocken outaclr Single-Port Memory (1) Simple Dual-Port Memory |
类似零件编号 - EP1C6F256I8 |
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类似说明 - EP1C6F256I8 |
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