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EP1C6Q144I8 数据表(PDF) 59 Page - Altera Corporation

部件名 EP1C6Q144I8
功能描述  Cyclone FPGA Family
Download  94 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1C6Q144I8 数据表(HTML) 59 Page - Altera Corporation

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Altera Corporation
59
Preliminary Information
Cyclone FPGA Family Data Sheet
LVDS I/O Pins
A subset of pins in all four I/O banks supports LVDS interfacing. These
dual-purpose LVDS pins require an external-resistor network at the
transmitter channels in addition to 100-
Ω termination resistors on receiver
channels. These pins do not contain dedicated serialization or
deserialization circuitry; therefore, internal logic performs serialization
and deserialization functions.
Table 16 shows the total number of supported LVDS channels per device
density.
Note to Table 16:
(1)
EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O
standard.
MultiVolt I/O Interface
The Cyclone architecture supports the MultiVolt I/O interface feature,
which allows Cyclone devices in all packages to interface with systems of
different supply voltages. The devices have one set of VCC pins for
internal operation and input buffers (VCCINT), and four sets for I/O
output drivers (VCCIO).
Table 16. Cyclone Device LVDS Channels
Device
Pin Count
Number of LVDS Channels
EP1C3
100
(1)
144
34
EP1C4
324
103
400
129
EP1C6
144
29
240
72
256
72
EP1C12
240
66
256
72
324
103
EP1C20
324
95
400
129


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