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EP1C6F256C7 数据表(PDF) 58 Page - Altera Corporation |
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EP1C6F256C7 数据表(HTML) 58 Page - Altera Corporation |
58 / 94 page 58 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Figure 35. Cyclone I/O Banks Notes (1), (2) Notes to Figure 35: (1) Figure 35 is a top view of the silicon die. (2) Figure 35 is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations. Each I/O bank has its own VCCIO pins. A single device can support 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a different standard with different I/O voltages. Each bank also has dual- purpose VREF pins to support any one of the voltage-referenced standards (e.g., SSTL-3) independently. If an I/O bank does not use voltage-referenced standards, the VREF pins are available as user I/O pins. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. I/O Bank 2 I/O Bank 3 I/O Bank 4 I/O Bank 1 All I/O Banks Support ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS ■ LVDS ■ SSTL-2 Class I and II ■ SSTL-3 Class I and II I/O Bank 3 Also Supports the 3.3-V PCI I/O Standard I/O Bank 1 Also Supports the 3.3-V PCI I/O Standard Individual Power Bus |
类似零件编号 - EP1C6F256C7 |
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类似说明 - EP1C6F256C7 |
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