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EP1C6Q144C7 数据表(PDF) 84 Page - Altera Corporation |
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EP1C6Q144C7 数据表(HTML) 84 Page - Altera Corporation |
84 / 94 page 84 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Tables 55 through 56 show the external timing parameters on column and row pins for EP1C12 devices. Table 55. EP1C12 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max tINSU 2.187 2.363 2.535 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 3.965 2.000 4.401 2.000 4.845 ns tXZ 5.592 6.192 6.798 ns tZX 5.592 6.192 6.798 ns tINSUPLL 1.152 1.260 1.368 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 1.943 0.500 2.142 0.500 2.344 ns tXZPLL 3.570 3.933 4.297 ns tZXPLL 3.570 3.933 4.297 ns Table 56. EP1C12 Row Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max tINSU 2.308 2.502 2.694 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 3.827 2.000 4.243 2.000 4.666 ns tXZ 5.413 5.988 6.570 ns tZX 5.413 5.988 6.570 ns tINSUPLL 1.273 1.399 1.527 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 1.805 0.500 1.984 0.500 2.165 ns tXZPLL 3.391 3.729 4.069 ns tZXPLL 3.391 3.729 4.069 ns |
类似零件编号 - EP1C6Q144C7 |
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类似说明 - EP1C6Q144C7 |
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