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EP1C6Q100I6 数据表(PDF) 81 Page - Altera Corporation

部件名 EP1C6Q100I6
功能描述  Cyclone FPGA Family
Download  94 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1C6Q100I6 数据表(HTML) 81 Page - Altera Corporation

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Altera Corporation
81
Preliminary Information
Cyclone FPGA Family Data Sheet
Tables 49 through 50 show the external timing parameters on column and
row pins for EP1C3 devices.
Table 49. EP1C3 Column Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.496
2.715
2.935
ns
tINH
0.000
0.000
0.000
ns
tOUTCO
2.000
3.656
2.000
4.049
2.000
4.445
ns
tXZ
5.283
5.840
6.398
ns
tZX
5.283
5.840
6.398
ns
tINSUPLL
1.195
1.308
1.421
ns
tINHPLL
0.000
0.000
0.000
ns
tOUTCOPLL
0.500
1.900
0.500
2.094
0.500
2.291
ns
tXZPLL
3.527
3.885
4.244
ns
tZXPLL
3.527
3.885
4.244
ns
Table 50. EP1C3 Row Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.574
2.806
3.041
ns
tINH
0.000
0.000
0.000
ns
tOUTCO
2.000
3.561
2.000
3.939
2.000
4.319
ns
tXZ
5.147
5.684
6.223
ns
tZX
5.147
5.684
6.223
ns
tINSUPLL
1.273
1.399
1.527
ns
tINHPLL
0.000
0.000
0.000
ns
tOUTCOPLL
0.500
1.805
0.500
1.984
0.500
2.165
ns
tXZPLL
3.391
3.729
4.069
ns
tZXPLL
3.391
3.729
4.069
ns


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