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EP1C20F400C6 数据表(PDF) 7 Page - Altera Corporation |
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EP1C20F400C6 数据表(HTML) 7 Page - Altera Corporation |
7 / 94 page Altera Corporation 7 Preliminary Information Cyclone FPGA Family Data Sheet LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM blocks from the left and right can also drive an LAB’s local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 3 shows the direct link connection. Figure 3. Direct Link Connection LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. LAB Direct link interconnect to right Direct link interconnect from right LAB, M4K memory block, PLL, or IOE output Direct link interconnect from left LAB, M4K memory block, PLL, or IOE output Local Interconnect Direct link interconnect to left |
类似零件编号 - EP1C20F400C6 |
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类似说明 - EP1C20F400C6 |
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