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EP1C6Q144C6 数据表(PDF) 83 Page - Altera Corporation |
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EP1C6Q144C6 数据表(HTML) 83 Page - Altera Corporation |
83 / 94 page Altera Corporation 83 Preliminary Information Cyclone FPGA Family Data Sheet Tables 53 through 54 show the external timing parameters on column and row pins for EP1C6 devices. Table 53. EP1C6 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max tINSU 2.432 2.643 2.853 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 3.720 2.000 4.121 2.000 4.527 ns tXZ 5.347 5.912 6.480 ns tZX 5.347 5.912 6.480 ns tINSUPLL 1.188 1.301 1.414 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 1.907 0.500 2.101 0.500 2.298 ns tXZPLL 3.534 3.892 4.251 ns tZXPLL 3.534 3.892 4.251 ns Table 54. EP1C6 Row Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max tINSU 2.517 2.741 2.966 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 3.618 2.000 4.004 2.000 4.394 ns tXZ 5.204 5.749 6.298 ns tZX 5.204 5.749 6.298 ns tINSUPLL 1.273 1.399 1.527 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 1.805 0.500 1.984 0.500 2.165 ns tXZPLL 3.391 3.729 4.069 ns tZXPLL 3.391 3.729 4.069 ns |
类似零件编号 - EP1C6Q144C6 |
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类似说明 - EP1C6Q144C6 |
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