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EP1C20F400I7ES 数据表(PDF) 33 Page - Altera Corporation |
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EP1C20F400I7ES 数据表(HTML) 33 Page - Altera Corporation |
33 / 94 page Altera Corporation 33 Preliminary Information Cyclone FPGA Family Data Sheet Figure 20. Read/Write Clock Mode in Simple Dual-Port Mode Note (1) Note to Figure 20: (1) All registers shown except the rden register have asynchronous clear ports. Single-Port Mode The M4K memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 21. A single M4K memory block can support up to two single-port mode RAM blocks if each RAM block is less than or equal to 2K bits in size. 6 D ENA Q D ENA Q D ENA Q D ENA Q D ENA Q data[ ] D ENA Q wraddress[ ] address[ ] Memory Block 256 × 16 512 × 8 1,024 × 4 2,048 × 2 4,096 × 1 Data In Read Address Write Address Write Enable Read Enable Data Out rdclken wrclken wrclock rdclock wren rden 6 LAB Row Clocks To MultiTrack Interconnect D ENA Q byteena[ ] Byte Enable Write Pulse Generator |
类似零件编号 - EP1C20F400I7ES |
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类似说明 - EP1C20F400I7ES |
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