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EP1C20F400C7ES 数据表(PDF) 37 Page - Altera Corporation |
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EP1C20F400C7ES 数据表(HTML) 37 Page - Altera Corporation |
37 / 94 page Altera Corporation 37 Preliminary Information Cyclone FPGA Family Data Sheet Figure 24. I/O Clock Regions PLLs Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as outputs for differential I/O support. Cyclone devices contain two PLLs, except for the EP1C3 device, which contains one PLL. Column I/O Clock Region IO_CLK[5..0] Column I/O Clock Region IO_CLK[5..0] 6 6 I/O Clock Regions I/O Clock Regions 8 Global Clock Network Row I/O Regions Cyclone Logic Array 6 6 LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] 6 6 6 6 |
类似零件编号 - EP1C20F400C7ES |
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类似说明 - EP1C20F400C7ES |
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