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EP1C6Q400 数据表(PDF) 76 Page - Altera Corporation

部件名 EP1C6Q400
功能描述  Cyclone FPGA Family
Download  94 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1C6Q400 数据表(HTML) 76 Page - Altera Corporation

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76
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 37 shows the memory waveforms for the M4K timing parameters
shown in Table 42.
Figure 37. Dual-Port RAM Timing Microparameter Waveform
Table 43. Routing Delay Internal Timing Microparameter Descriptions
Symbol
Parameter
tR4
Delay for an R4 line with average loading; covers a distance
of four LAB columns
tC4
Delay for an C4 line with average loading; covers a distance
of four LAB rows
tLOCAL
Local interconnect delay
wrclock
wren
wraddress
data-in
reg_data-out
an-1
an
a0
a1
a2
a3
a4
a5
din-1
din
din4
din5
rdclock
a6
din6
unreg_data-out
rden
rdaddress
bn
b0
b1
b2
b3
doutn-2
doutn-1
doutn
doutn-1
doutn
dout0
tWERESU
tWEREH
tDATACO1
tDATACO2
tDATASU
tDATAH
tWEREH
tWERESU
tWADDRSU
tWADDRH
dout0
tRC


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