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M378T3354CZ3 Datasheet(数据表) 2 Page - Samsung semiconductor

部件型号  M378T3354CZ3
说明  DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb C-die 64/72-bit Non-ECC/ECC
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制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
标志 SAMSUNG - Samsung semiconductor

M378T3354CZ3 Datasheet(HTML) 2 Page - Samsung semiconductor

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Rev. 1.2 Aug. 2005
256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
DDR2 Unbuffered DIMM Ordering Information
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Part Number
Density
Organization
Component Composition
Number of Rank
Height
x64 Non ECC
M378T3354CZ3-CE7/E6/D5/CC
256MB
32Mx64
32Mx16(K4T51163QC)*4
1
30mm
M378T3354CZ0-CE7/E6/D5/CC
256MB
32Mx64
32Mx16(K4T51163QC)*4
1
30mm
M378T6553CZ3-CE7/E6/D5/CC
512MB
64Mx64
64Mx8(K4T51083QC)*8
1
30mm
M378T6553CZ0-CE7/E6/D5/CC
512MB
64Mx64
64Mx8(K4T51083QC)*8
1
30mm
M378T2953CZ3-CE7/E6/D5/CC
1GB
128Mx64
64Mx8(K4T51083QC)*16
2
30mm
M378T2953CZ0-CE7/E6/D5/CC
1GB
128Mx64
64Mx8(K4T51083QC)*16
2
30mm
x72 ECC
M391T6553CZ3-CE7/E6/D5/CC
512MB
64Mx72
64Mx8(K4T51083QC)*9
1
30mm
M391T6553CZ0-CE7/E6/D5/CC
512MB
64Mx72
64Mx8(K4T51083QC)*9
1
30mm
M391T2953CZ3-CE7/E6/D5/CC
1GB
128Mx72
64Mx8(K4T51083QC)*18
2
30mm
M391T2953CZ0-CE7/E6/D5/CC
1GB
128Mx72
64Mx8(K4T51083QC)*18
2
30mm
Features
• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
•VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
- support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
E7 (DDR2-800)
E6 (DDR2-667)
D5 (DDR2-533)
CC (DDR2-400)
Unit
Speed@CL3
400
400
400
400
Mbps
Speed@CL4
533
533
533
400
Mbps
Speed@CL5
800
667
533
-Mbps
CL-tRCD-tRP
5-5-5
5-5-5
4-4-4
3-3-3
CK
Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
64Mx8(512Mb) based Module
A0-A13
A0-A9
BA0-BA1
A10
32Mx16(512Mb) based Module
A0-A12
A0-A9
BA0-BA1
A10




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