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Z86E0812PSC1866 数据表(PDF) 21 Page - Zilog, Inc. |
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Z86E0812PSC1866 数据表(HTML) 21 Page - Zilog, Inc. |
21 / 38 page Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification 16 Option Bit Modes Table 10 lists the device’s available option bits and their default states. OPTION BIT PROGRAM AND VERIFY Mode Entry 1. To enter OPTION BIT PROGRAM AND VERIFY mode, all pins must be set as per Table 11. The initial state for VPP and CLEAR is VIL while OE is at VIH. 2. VPP is raised to VIH. 3. CLEAR is pulsed High to VIH, then Low to VIL. See Table 14 for specifications regarding the CLEAR signal. 4. VPP is lowered to VIL. 5. After a delay of at least 1µs minimum, VPP is raised to VIH. NC Pin 6 Pin 7 No Connection OE Pin 8 Pin 9 See Figure 10 EPM Pin 9 Pin 10 VIH VPP Pin 10 Pin 11 VIH CLEAR Pin 11 Pin 12 See Figure 10 CLOCK Pin 12 Pin 13 See Figure 10 PGM Pin 13 Pin 14 See Figure 10 Table 10. Option Bit Values* Bit Option Unprogrammed Default Value D0 ROM Protect Disabled D1 Low-EMI Mode Disabled D2 Autolatches Enabled D3 Reserved Must be 1 D4 Permanent WDT Disabled D5 Reserved Must be 1 D6 RC Oscillator Disabled D7 32-kHz Oscillator Disabled Note: Option bits are 0 when programmed and 1 when unprogrammed. Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions (Continued) |
类似零件编号 - Z86E0812PSC1866 |
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类似说明 - Z86E0812PSC1866 |
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