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BD86852MUF-C 数据表(PDF) 21 Page - Rohm |
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BD86852MUF-C 数据表(HTML) 21 Page - Rohm |
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21 / 46 page  21/43 TSZ02201-0A3A0AP00520-1-2 © 2020 ROHM Co., Ltd. All rights reserved. 03.Mar.2020 Rev.001 www.rohm.com TSZ22111 • 15 • 001 BD86852MUF-C Function Explanations – continued Timing Chart of Start and Stop using EN (B-mode) VCC Internal SS3 (DC/DC3) VO3 (DC/DC3) Internal SS2 (DC/DC2) VO2 (DC/DC2) VO4 (EXT_LDO) = FB_LDO PG OOD VTH_EN1 VUVLOVREG_OFF VO2 discharge VO3 discharge VLVD32 VLVD42 VLVD21 VLVD31 VTH_EN2 EN VREG Internal SS1 (DC/DC1) VLVD22 SS3 finish 4576 clk SS2 finish 4576 clk VO1 (DC/DC1) = VS2, VS3, VS4 200 μs (Typ) SS1 finish 4576 clk EN_LDO tPG OOD = 10 ms VLVD12 VUVLOVS_OFF VLVD41 Figure 19. Output Timing Chart (EN Start-up and Stop) Output power up sequence 1. EN high input -> Internal regulator (VREG) starts up -> VREG power good. 2. VO1 (DC/DC1) starts up -> VO1 power good (VO1 > VLVD12), UVLO_VS is canceled and internal SS1 is up. 3. EN_LDO is up -> VO4 (External LDO) power good (VO4 > VLVD42). 4. VO3 (DC/DC3) starts up -> VO3 power good (VO3 > VLVD32), and internal SS3 is up. 5. VO2 (DC/DC2) starts up -> VO2 power good (VO2 > VLVD22), and internal SS2 is up. 6. Wait 10 ms (Typ) -> PGOOD is up (released). The “10 ms” time depends on fOSC2. Output power down sequence 1. EN low input -> PGOOD low -> stop VO2 (DC/DC2) operation and discharging VO2. 2. LVD2 power bad or 10 ms (Typ) after VO2 discharge start -> stop VO3 (DC/DC3) operation and start discharging VO3. 3. LVD3 power bad or 10 ms (Typ) after VO3 discharge start -> VO4 (External LDO) falls. 4. LVD4 power bad or 10 ms (Typ) after EN_LDO low -> stop VO1 (DC/DC1) operation including the internal regulators (VREG). PGOOD operation is dependent on LVD1 to 4 conditions. The “10 ms” time depends on fOSC2. |
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类似说明 - BD86852MUF-C |
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