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CY7C1310AV18 数据表(PDF) 4 Page - Cypress Semiconductor

部件名 CY7C1310AV18
功能描述  18-Mb QDR-II SRAM 2-Word Burst Architecture
Download  21 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1310AV18 数据表(HTML) 4 Page - Cypress Semiconductor

  CY7C1310AV18 Datasheet HTML 1Page - Cypress Semiconductor CY7C1310AV18 Datasheet HTML 2Page - Cypress Semiconductor CY7C1310AV18 Datasheet HTML 3Page - Cypress Semiconductor CY7C1310AV18 Datasheet HTML 4Page - Cypress Semiconductor CY7C1310AV18 Datasheet HTML 5Page - Cypress Semiconductor CY7C1310AV18 Datasheet HTML 6Page - Cypress Semiconductor CY7C1310AV18 Datasheet HTML 7Page - Cypress Semiconductor CY7C1310AV18 Datasheet HTML 8Page - Cypress Semiconductor CY7C1310AV18 Datasheet HTML 9Page - Cypress Semiconductor Next Button
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CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Document #: 38-05497 Rev. *A
Page 4 of 21
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1310AV18 - D[7:0]
CY7C1312AV18 - D[17:0]
CY7C1314AV18 - D[35:0]
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3
− active LOW. Sampled on the rising edge of the K and
K clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1310AV18
− BWS0 controls D[3:0] and BWS1 controls D[7:4].
CY7C1312AV18
− BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1314AV18
− BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]
and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K (read address) and K (write
address) clocks during active read and write operations. These address inputs are multi-
plexed for both Read and Write operations. Internally, the device is organized as 2M x 8
(2 arrays each of 1M x 8) for CY7C1310AV18, 1M x 18 (2 arrays each of 512K x 18) for
CY7C1312AV18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314AV18.
Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1310AV18, 19 address inputs for CY7C1312AV18 and 18 address inputs for
CY7C1314AV18. These inputs are ignored when the appropriate port is deselected.
Pin Configurations (continued)
23
4
56
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
Q27
D27
D28
D34
DOFF
Q33
VSS/288M NC/72M
BWS2
K
WPS
BWS1
Q18
D18
Q30
D31
D33
TDO
Q28
D29
D22
D32
Q34
Q31
TCK
D35
D19
A
BWS3
K
BWS0
VSS
AA
A
Q19
VSS
VSS
VSS
VSS
VDD
A
VSS
VSS
VSS
VDD
Q20
D21
VDDQ
D23
Q23
D25
Q25
Q26
A
VDDQ
VSS
VDDQ
VDD
VDD
Q22
VDDQ
VDD
VDDQ
VDD
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VSS
VSS
VSS
VSS
A
A
C
VSS
A
A
A
D20
VSS
Q29
VSS
Q21
D30
VREF
VSS
VDD
VSS
VSS
A
VSS
C
Q32
Q24
Q35
D26
D24
VDD
A
89
10
11
Q0
NC/36M VSS/144M
RPS
CQ
A
D17
Q17
Q8
VSS
D16
Q7
D8
Q16
VSS
D15
Q6
D5
D9
Q14
VREF
Q11
Q3
VDDQ
Q15
VDDQ
D14
Q5
VDDQ
VDDQ
VDDQ
D4
VDDQ
D12
Q4
Q12
VDDQ
VDDQ
D11
VSS
D10
D2
Q10
TDI
TMS
VSS
A
Q9
A
D7
D6
D13
ZQ
D3
Q2
D1
Q1
D0
Q13
A
CY7C1314AV18 (512k × 36) – 11 × 15 BGA


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